| 王秀敏,张洋,付娟,王尧.基于FPGA的WIMAX LDPC码译码器设计与实现[J].,2012,(4):594-598 |
| 基于FPGA的WIMAX LDPC码译码器设计与实现 |
| Design and implementation of WIMAX LDPC code decoder based on FPGA |
| |
| DOI：10.7511/dllgxb201204021 |
| 中文关键词: WIMAX 低密度奇偶校验码译码器 现场可编程逻辑门阵列 TDMP 归一化最小和算法 |
| 英文关键词: WIMAX low density parity-check (LDPC) code decoder field programmable gate array (FPGA) TDMP normalized minimum sum (NMS) algorithm |
| 基金项目:国家质检总局科技计划资助项目(2009QK027);浙江省科技计划优先主题重点工业项目(2010C11024);国家自然科学基金青年基金资助项目(200802025). |
|
| 摘要点击次数: 1388 |
| 全文下载次数: 709 |
| 中文摘要: |
| 提出了基于TDMP-NMS算法的部分并行LDPC码译码器结构,其具有TDMP算法译码收敛快和NMS算法保持较好误码率性能下实现简单的优点．该译码器支持WIMAX标准中所有码长和码率LDPC码的译码．设计了一种基于桶形移位寄存器的重组网络单元,实现了对该标准中19种码长LDPC 码译码的支持．采用一种适合于TDMP算法及其各种简化算法的动态迭代停止准则,使译码器能根据译码情况自适应地调整迭代次数．结果显示所提方案在提高译码器吞吐率的同时有效减少了译码器的硬件资源消耗． |
| 英文摘要: |
| A partial parallel low density parity-check (LDPC) code decoder architecture based on turbo decoding message passing (TDMP)-normalized minimun sum (NMS) algorithm is proposed, which can not only achieve a convergence speed as high as TDMP algorithm, but also possess the easy-to-implement advantage of NMS algorithm while keeping a good bit error rate (BER) performance. The decoder supports the decoding of LDPC code of any code rate and code length defined in WIMAX standard. A barrel shifter-based shuffle network is designed which enables the decoder to support all the 19 code lengths. A dynamic iteration stopping criterion suitable for TDMP algorithm and its simplified version is employed with which the decoder can adjust the iteration number according to the decoding state adaptively. Experimental results show that the schemes proposed reduce the hardware cost as well as improve the throughput of the decoder effectively. |
|
查看全文
查看/发表评论 下载PDF阅读器 |
| 关闭 |